The present invention relates to a circuit for arithmetic operations and, more particularly, to an absolute value calculating circuit for producing the absolute value of a difference between two numerical values.
To code video signals, for example, arithmetic operations are frequently performed for rapidly producing the absolute value of a difference between two numerical values. An absolute value calculating circuit (referred to simply as a calculating circuit hereinafter) has been proposed in various forms in order to implement such arithmetic operations. Most of prior art calculating circuits are of the type reported by Yamashina et al in a paper entitled "A Realtime Microprogrammable Video Signal LSI" at IEEE International Solid-State Circuits Conference held at GRAND BALLROOM WEST, New York City, on Feb. 26, 1987, SESSION XV: HIGH-SPEED SIGNAL PROCESSORS, THPM 15.3. A calculating circuit of the type described in this paper has a parallel connection of two adders (or subtractors), and a selector. Assuming two input values a and b, one of the adders produces (a-b) and the other produces (b-a), and the selector selects the value of a result of calculation which is positive. A drawback with this type of calculating circuit is that the use of two adders (or subtractors) makes the construction complicated, adds to the number of circuit elements, requires a substantial area on an integrated circuit, and aggravates power consumption.